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3968
A3968SLB (SOIC)
OUT1A INPUT1A INPUT1B GROUND SENSE 1 OUT 1B LOAD SUPPLY REFERENCE 1 V 2 3 4 5 6 7 8 V VBB V CC RC LOGIC LOGIC
BB
DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE
The A3968SA and A3968SLB are designed to bidirectionally control two dc motors. Each device includes two H-bridges capable of continuous output currents of 650 mA and operating voltages to 30 V. Motor winding current can be controlled by the internal fixed-frequency, pulse-width modulated (PWM), current-control circuitry. The peak load current limit is set by the user's selection of a reference voltage and current-sensing resistors. Except for package style and pinout, the two devices are identical. The fixed-frequency pulse duration is set by a user-selected external RC timing network. The capacitor in the RC timing network also determines a user-selectable blanking window that prevents false triggering of the PWM current-control circuitry during switching transitions. To reduce on-chip power dissipation, the H-bridge power outputs have been optimized for low saturation voltages. The sink drivers feature Allegro's patented SatlingtonTM output structure. The Satlington outputs combine the low voltage drop of a saturated transistor and the high peak current capability of a Darlington. For each bridge, the INPUTA and INPUTB terminals determine the load current polarity by enabling the appropriate source and sink driver pair. When a logic low is applied to both INPUTs of a bridge, the braking function is enabled. In brake mode, both source drivers are turned OFF and both sink drivers are turned ON, thereby dynamically braking the motor. When a logic high is applied to both INPUTs of a bridge, all output drivers are disabled. Special power-up sequencing is not required. Internal circuit protection includes thermal shutdown with hysteresis, ground-clamp and flyback diodes, and crossover-current protection. The A3968SA is supplied in a 16-pin dual in-line plastic package. The A3968SLB is supplied in a 16-lead plastic SOIC with copper heat sink tabs. The power tab is at ground potential and needs no electrical isolation.
Data Sheet 29319.29
16 15 14 13 12 11 10 9
OUT 2A INPUT2A INPUT2B GROUND SENSE 2 OUT 2B LOGIC SUPPLY RC
REF
Dwg. PP-066
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, VBB ................... 30 V Output Current, IOUT (peak) .......... 750 mA (continuous) .............................. 650 mA Logic Supply Voltage, VCC ................. 7.0 V Input Voltage, Vin ..... -0.3 V to VCC + 0.3 V Sense Voltage, VS ................................ 1.0 V Package Power Dissipation (TA = 25C), PD A3968SA ..................................... 1.8 W* A3968SLB ................................... 1.4 W* Operating Temperature Range, TA ................................... -20C to +85C Junction Temperature, TJ ................................................. +150C Storage Temperature Range, TS ................................. -55C to +150C
Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150C. * Per SEMI G42-88 Specification, Thermal Test Board Standardization for Measuring Junctionto-Ambient Thermal Resistance of Semiconductor Packages.
FEATURES
s s s s s s s s s 650 mA Continuous Output Current 30 V Output Voltage Rating Internal Fixed-Frequency PWM Current Control SatlingtonTM Sink Drivers Brake Mode User-Selectable Blanking Window Internal Ground-Clamp & Flyback Diodes Internal Thermal-Shutdown Circuitry Crossover-Current Protection and UVLO Protection
Always order by complete part number:
Part Number A3968SA A3968SLB Package 16-pin DIP 16-lead batwing SOIC RJA 68C/W 90C/W RJC 38C/W -- RJT -- 6C/W
3968 DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE
FUNCTIONAL BLOCK DIAGRAM
(one-half of circuit shown)
LOGIC SUPPLY LOAD SUPPLY OUTA OUTB
INPUTA
V CC
+
V BB
UVLO & TSD
INPUTB
SOURCE ENABLE
BLANKING GATE CURRENT-SENSE COMPARATOR
CONTROL LOGIC
SENSE
TO OTHER BRIDGE /4
PWM LATCH R Q S
+ -
TO OTHER BRIDGE
GROUND RC
OSC TO OTHER BRIDGE
RS
RT
CT
REFERENCE
Dwg. FP-036-4
A3968SA (DIP)
SENSE 1 OUT 1B LOAD SUPPLY REFERENCE RC LOGIC SUPPLY OUT 2B SENSE 2 1 16 INPUT1B INPUT1A OUT 1A GROUND GROUND OUT 2A INPUT 2A INPUT 2B
TRUTH TABLE
INPUTA L L H H INPUTB L H L H OUTA L L H Z OUTB L H L Z Description Brake mode "Forward" "Reverse" Disable
2 3 4 5 6 7 8 V REF RC V
LOGIC
15 14
V BB
13 12 11
Z = High impedance
CC
LOGIC
10 9
Dwg. PP-066-3
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 1997, 2003 Allegro MicroSystems, Inc.
3968 DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE
ELECTRICAL CHARACTERISTICS at TA = +25C, VBB = 30 V, VCC = 4.75 V to 5.5 V, VREF = 2 V, VS = 0 V, 56 k & 680 pF RC to Ground (unless noted otherwise)
Limits Characteristic Output Drivers
Load Supply Voltage Range Output Leakage Current VBB ICEX Operating, IOUT = 650 mA, L = 3 mH VOUT = 30 V VOUT = 0 V Output Saturation Voltage VCE(SAT) Source Driver, IOUT = -400 mA Source Driver, IOUT = -650 mA Sink Driver, IOUT = +400 mA, VS = 0.5 V Sink Driver, IOUT = +650 mA, VS = 0.5 V Clamp Diode Forward Voltage VF IF = 400 mA IF = 650 mA Motor Supply Current (No Load) IBB(ON) IBB(OFF) Both bridges ON (forward or reverse) All INPUTs = 2.4 V VCC -- -- -- -- -- -- -- -- -- -- -- <1.0 <-1.0 1.7 1.8 0.3 0.7 1.1 1.4 3.0 <1.0 30 50 -50 2.0 2.1 0.5 1.3 1.4 1.6 5.0 200 V A A V V V V V V mA A
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Control Logic
Logic Supply Voltage Range Logic Input Voltage VCC VIN(1) VIN(0) Logic Input Current IIN(1) IIN(0) Reference Input Volt. Range Reference Input Current Reference Divider Ratio Current-Sense Comparator Input Offset Voltage Current-Sense Comparator Input Voltage Range Sense-Current Offset VREF IREF VREF/VTRIP VIO VS ISO VREF = 0.1 V Operating IS - IOUT, 50 mA IOUT 650 mA VIN = 2.4 V VIN = 0.8 V Operating Operating 4.75 2.4 -- -- -- 0.1 -2.5 3.8 -6.0 -0.3 12 -- -- -- <1.0 <-20 - 0 4.0 0 -- 18 5.50 -- 0.8 20 -200 2.0 1.0 4.2 6.0 1.0 24 V V V A A V A -- mV V mA
NOTES:1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal.
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3968 DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE
ELECTRICAL CHARACTERISTICS at TA = +25C, VBB = 30 V, VCC = 4.75 V to 5.5 V, VREF = 2 V, VS = 0 V, 56 k & 680 pF RC to Ground (unless noted otherwise) (cont.)
Limits Characteristic Control Logic (continued)
PWM RC Frequency PWM Propagation Delay Time fosc tPWM CT = 680 pF, RT = 56 k Comparator Trip to Source OFF Cycle Reset to Source ON Cross-Over Dead Time Propagation Delay Times tcodt tpd 1 k Load to 25 V IOUT = 650 mA, 50% to 90%: Disable OFF to Source ON Disable ON to Source OFF Disable OFF to Sink ON Disable ON to Sink OFF Brake Enable to Sink ON Brake Enable to Source OFF 22.9 -- -- 0.2 -- -- -- -- -- -- -- -- Increasing VCC Both bridges ON (forward or reverse) All INPUTs = 2.4 V All INPUTs = 0.8 V -- 0.1 -- -- -- 25.4 1.0 0.8 1.8 100 500 200 200 2200 200 165 15 4.1 0.6 -- -- -- 27.9 1.4 1.2 3.0 -- -- -- -- -- -- -- -- 4.6 -- 50 9.0 95 kHz s s s ns ns ns ns ns ns C C V V mA mA mA
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis Logic Supply Current
TJ TJ VT(UVLO)+ VT(UVLO)hys ICC(ON) ICC(OFF) ICC(BRAKE)
NOTES:1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3968 DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE
FUNCTIONAL DESCRIPTION
Internal PWM Current Control. The A3968SA and A3968SLB dual H-bridges are designed to bidirectionally control two dc motors. An internal fixed-frequency PWM current-control circuit controls the load current in each motor. The current-control circuitry works as follows: when the outputs of the H-bridge are turned on, current increases in the motor winding. The load current is sensed by the current-control comparator via an external sense resistor (RS). Load current continues to increase until it reaches the predetermined value, set by the selection of external current-sensing resistors and reference input voltage (VREF) according to the equation: ITRIP = IOUT + ISO = VREF/(4RS) where ISO is the sense-current error (typically 18 mA) due to the base-drive current of the sink driver transistor. At the trip point, the comparator resets the sourceenable latch, turning off the source driver of that H-bridge. The source turn off of one H-bridge is independent of the other H-bridge. Load inductance causes the current to recirculate through the sink driver and ground-clamp diode. The current decreases until the internal clock oscillator sets the source-enable latches of both H-bridges, turning on the source drivers of both bridges. Load current increases again, and the cycle is repeated. The frequency of the internal clock oscillator is set by
INPUT A
the external timing components RTCT. The frequency can be approximately calculated as: fosc = 1/(RT CT + tblank) where tblank is defined below. The range of recommended values for RT and CT are 20 k to 100 k and 470 pF to 1000 pF respectively. Nominal values of 56 k and 680 pF result in a clock frequency of 25.4 kHz. Current-Sense Comparator Blanking. When the source driver is turned on, a current spike occurs due to the reverse-recovery currents of the clamp diodes and switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source enable latch, the current-control comparator output is blanked for a short period of time when the source driver is turned on. The blanking time is set by the timing component CT according to the equation: tblank = 1900 CT (s). A nominal CT value of 680 pF will give a blanking time of 1.3 s. The current-control comparator is also blanked when the load current changes polarity (direction or phase change). This internally generated blank time is approximately 1.8 s.
V BB
INPUT B
"FORWARD" BRIDGE ON ALL OFF
"REVERSE"
+ I OUTB 0 -
BRIDGE ON SOURCE OFF ALL OFF
BRIDGE ON td
I TRIP
SOURCE OFF
RTC T
INTERNAL OSCILLATOR
t blank
RS
Dwg. WM-003-3
Dwg. EP-006-16
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3968 DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE
FUNCTIONAL DESCRIPTION (continued)
Load Current Regulation. Due to internal logic and switching delays (td), the actual load current peak may be slightly higher than the ITRIP value. These delays, plus the blanking time, limit the minimum value the current control circuitry can regulate. To produce zero current in a winding, the INPUTA and INPUTB terminals should be held high, turning off all output drivers for that H-bridge. Logic Inputs. The direction of current in the motor winding is determined by the state of the INPUTA and INPUTB terminals of each bridge (see Truth Table). An internally generated dead time (tcodt) of approximately 1.8 s prevents cross-over current spikes that can occur when switching the motor direction. A logic high on both INPUTs turns off all four output drivers of that H-bridge. This results in a fast current decay through the internal ground clamp and flyback diodes. The appropriate INPUTA or INPUTB can be pulsewidth modulated for applications that require a fast current-decay PWM. The internal current-control logic can be disabled by connecting the RTCT terminal to ground. A logic low on the INPUTA and the INPUTB terminals will place that H-Bridge in the brake mode. Both source drivers are turned OFF and both sink drivers are turned ON. This has the effect of shorting the dc motor's backEMF voltage, resulting in a current flow that dynamically brakes the motor. Note that during braking the internal current-control circuitry is disabled. Therefore, care should be taken to ensure that the motor's current does not exceed the absolute maximum rating of the A3968. The REFERENCE input voltage is typically set with a resistor divider from VCC. This reference voltage is internally divided down by 4 to set up the current-comparator trip-voltage threshold. The reference input voltage range is 0 to 2 V. Output Drivers. To minimize on-chip power dissipation, the sink drivers incorporate a SatlingtonTM structure. The Satlington output combines the low VCE(sat) features of a saturated transistor and the high peak-current capability of a Darlington (connected) transistor. A graph showing typical output saturation voltages as a function of output current is on the next page. Miscellaneous Information. Thermal protection circuitry turns off all output drivers should the junction temperature reach +165C (typical). This is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Normal operation is resumed when the junction temperature has decreased about 15C. The A3968 current control employs a fixed-frequency, variable duty cycle PWM technique. If the duty cycle exceeds 50%, the current-control-regulation frequency may change. To minimize current-sensing inaccuracies caused by ground trace IR drops, each current-sensing resistor should have a separate return to the ground terminal of the device. For low-value sense resistors, the I x R drops in the printed-wiring board can be significant and should be taken into account. The use of sockets should be avoided as their contact resistance can cause variations in the effective value of RS. The LOAD SUPPLY terminal, VBB, should be decoupled with an electrolytic capacitor (47 F recommended) placed as close to the device as physically practical. To minimize the effect of system ground I x R drops on the logic and reference input signals, the system ground should have a low-resistance return to the load supply voltage. The frequency of the clock oscillator will determine the amount of ripple current. A lower frequency will result in higher current ripple, but reduced heating in the motor and driver IC due to a corresponding decrease in hysteretic core losses and switching losses respectively. A higher frequency will reduce ripple current, but will increase switching losses and EMI.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3968 DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE
2.5
OUTPUT SATURATION VOLTAGE IN VOLTS
TA = +25C 2.0 SOURCE DRIVER 1.5
Typical output saturation voltages showing SatlingtonTM sink-driver operation.
1.0
0.5 SINK DRIVER
0 200 300 400
500
600
700
Dwg. GP-064-1A
OUTPUT CURRENT IN MILLIAMPERES
TYPICAL APPLICATION
MOTOR 1 1 INPUT1A INPUT1B V 2 3 4 0.5 5 +5 V 6 11 V BB V 10 9 +5 V +24 V 7 8 VREF 12 LOGIC LOGIC
BB
MOTOR 2 16 15 14 13 0.5 INPUT2A INPUT2B
39 k
CC
RC
10 k
Dwg. EP-047-6
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56 k
47 F
680 pF
+
3968 DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE
A3968SA (DIP)
Dimensions in Inches (controlling dimensions)
16 9 0.014 0.008
0.430 0.280 0.240
MAX
0.300
BSC
1 0.070 0.045
0.100 0.775 0.735
BSC
8 0.005
MIN
0.210
MAX
0.015
MIN
0.150 0.115 0.022 0.014
Dwg. MA-001-16A in
Dimensions in Millimeters (for reference only)
16 9 0.355 0.204
10.92 7.11 6.10
MAX
7.62
BSC
1 1.77 1.15
2.54 19.68 18.67
BSC
8 0.13
MIN
5.33
MAX
0.39
MIN
3.81 2.93 0.558 0.356
Dwg. MA-001-16A mm
NOTES:1. 2. 3. 4.
Exact body and lead configuration at vendor's option within limits shown. Lead spacing tolerance is non-cumulative. Lead thickness is measured at seating plane or below. Supplied in standard sticks/tubes of 25 devices.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3968 DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE
A3968SLB (SOIC)
Dimensions in Inches (for reference only)
16 9 0.0125 0.0091
0.2992 0.2914
0.419 0.394
0.050 0.016 0.020 0.013 1 2 3 0.4133 0.3977 0.050
BSC
0 TO 8
0.0926 0.1043 0.0040 MIN.
Dwg. MA-008-16A in
Dimensions in Millimeters (controlling dimensions)
16 9 0.32 0.23
7.60 7.40
10.65 10.00
1.27 0.40 0.51 0.33 1 2 3 10.50 10.10 1.27
BSC
0 TO 8
2.65 2.35 0.10 MIN.
Dwg. MA-008-16A mm
NOTES:1. 2. 3. 4.
Exact body and lead configuration at vendor's option within limits shown. Lead spacing tolerance is non-cumulative. Webbed lead frame. Leads 4 and 13 are internally one piece. Supplied in standard sticks/tubes of 47 devices, or add "TR" to part number for tape and reel.
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3968 DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

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